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- C. T. Chen, L. G. Chen, T. D. Chiueh, and J. H. Hsiao, “ An Efficient Pipelined VLSI Implementation of Rank Order Filter,” in International Symposium on Speech, Image Processing and Neural Networks, Hong Kong, pp.630-634, April 1994.
- J. H. Hsiao, L. G. Chen, T. D. Chiueh, and C. T. Chen, “ High Throughput CORDIC_Based Systolic Array Design for the Discrete Cosine Transform,” in Proceeding of IEEE International Symposium on Circuits and Systems, London, Vol. 2, pp. 85-88, May 1994.
- C. T. Chen, L. G. Chen, T. D. Chiueh, and J. H. Hsiao, “Design and VLSI Implementation of Real_Time Weighted Median Filter,” IEEE Asia-Pacific Conference on Circuits and Systems, Taipei, pp. 91-97, 1994.
- 蕭如宣,陳益華,李進華,“Optimization for Root Raised Cosine Filter Design“,電子通訊與應用研討會,2006。
- 蕭如宣,李進華,“Optimization for CORDIC-Based DCT Processor Design”,第一屆智慧生活科技研討會,2006。
- 蕭如宣,陳益華,王硯靖,李進華,”Implementation and Verification of WCDMA Uplink Transmitting and Receiving Modules in FPGA with Soft-IP Code”,第一屆智慧生活科技研討會,2006。
- 蕭如宣,陳彥承,洪文琪,” 數位電子樂譜雛型系統”,第五屆智慧生活科技研討會,2010。
- 蕭如宣,廖士弼,陳彥承,”互動健康電視”,第五屆智慧生活科技研討會,2010。
- 蕭如宣,蘇耿賢,”免招手智慧型公車站牌”, 2010年科技創新與智慧生活國際研討會,2010。
- 蕭如宣,陳建利,鄭文彥,”互動式模擬寵物”, 2010數位生活科技研討會,2010。
- 蕭如宣,蕭琪勝,”高速FPGA發展平台之訊號完整性設計”,第六屆智慧生活科技研討會,2011。
- 蕭如宣,曾智宏,”SRRC IP產生器設計與實作”,第六屆智慧生活科技研討會,2011。
- Yi Hua Chen, Jue Hsuan Hsiao, , Kun Feng Lin, and Chun Chun Yeh, “BPTC(196,96) Code Simulation and Implementation in C-code DSP Chip,” in International Conference on Consumer Electronics, Communications and Networks, Xianning, China, Vol. 6, pp.4833-4837, April. 2011.
- Yi Hua Chen, Jue Hsuan Hsiao, Pang Fu Liu, and Jheng-Shyuan He, “Golay(20,8) C Code Simulation and Implementation in DSP Chip,” in International Conference on Consumer Electronics, Communications and Networks, Xianning, China, Vol. 6 , pp.4990-4994, April. 2011.
- Yi Hua Chen, Jue Hsuan Hsiao, Pang Fu Liu, and Jheng-Shyuan He, “Simulation and Implementation of MSK with Golay Code in DSP Chip,” in 2011 Cross Strait Quad-Regional Radioo Sicence and Wireless Technology Conference, Harbin, China, Vol. 2 , pp.1586-1589, July. 2011.
- Jue Hsuan Hsiao, Chien Nan Lee, and Zhi Hong Tseng,, “Design and Implementation of LPF IP Generator,” in 2011 Cross Strait Quad-Regional Radioo Sicence and Wireless Technology Conference, Harbin, China, Vol. 2 , pp.1586-1589, July. 2011.
- Jue Hsuan Hsiao, Yi Hua Chen, Pang Fu Liu, and Kun Feng Lin, “Design and Implementation of SRRC IP Generator,” in 2nd International Workshop on Recent Advances in Broadband Access Networks, St. Petersburg, Russia, Vol. , pp. 800-804, Aug. 2011.
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1. J. H. Hsiao, L. G. Chen, T. D. Chiueh, and C. T. Chen, “ High Throughput CORDIC_Based Systolic Array Design for the Discrete Cosine Transform,” IEEE Transactions on Circuits and Systems for Video Technology, Vol. 5, No. 3, pp. 218~225, June 1995.
2. 蕭如宣,林奕辰,“一種快速雛型系統設計方法—以SoPC設計低頻段手持式頻譜分析儀 “,亞東學報25期,pp.1-7,2005。
3. 蕭如宣,李進華,“最佳化RRC濾波器設計 “,亞東學報26期,pp.23-32,2006。
4. 蕭如宣,李進華,“CORDIC Processor Design “,亞東學報26期,pp.13-19,2006。
5. 蕭如宣,陳益華,陳彥廷,陳世芳,許書銓,” W-CDMA系統之初始細胞搜尋之Soft-IP設計”,亞東學報27期,pp.13-22,2007。
6. 蕭如宣,陳彥廷, “觸控面板筆劃萃取之線上中文手寫辨識系統設計” ,亞東學報29期,pp.25-35,2009。
7. 蕭如宣,黃亞生,“簡易儲存式心電儀雛型系統設計”,亞東學報30期,pp.19-25,2010。
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